1. Field of the Invention
The present invention relates to a semiconductor device and a manufacturing method thereof, and more particularly, to a dynamic random access memory for avoiding a short circuit between adjacent storage nodes and a manufacturing method thereof.
2. Description of the Prior Art
Generally, the unit structure of dynamic random access memory (DRAM) is composed of a transistor and a capacitor configured to store charge for recording required data. As the applications increase, the size of DRAM has to be shrunk for increasing the DRAM integrity, enhancing the operation speed of the device, increasing the storage of the DRAM, and satisfying the demands from consumers for miniaturizing electronic devices.
In the general DRAM, transistors are formed in a substrate, and word lines are used to connect the transistors aligned in the same direction in series. Bit lines crossing the word lines are then formed on the transistors. For preventing the bit lines from being electrically connected with the word lines, storage node contacts may be connected to source/drain regions of the transistors via regions surrounded by any two adjacent word lines and any two adjacent bit lines. Subsequently, a storage node, a capacitance dielectric layer, and a top electrode of the capacitor may be sequentially formed on the each of the storage node contacts. For reducing the area of each capacitor in the chip as much as possible and keeping specific capacitance, the capacitors are formed to be higher and thinner. Therefore, openings with higher aspect ratio have to be formed on the storage node contacts in the step of forming the storage nodes, and each of the openings has to be formed corresponding to only one of the storage node contacts for forming the capacitor electrically connected to the corresponding storage node contact.
However, as the critical dimension becomes smaller and smaller, one opening with high aspect ratio may contact two storage node contacts because of the alignment shift in the photolithographic process, the storage node subsequently formed will be electrically connected with two adjacent storage node contacts, and the short circuit between the storage node contacts may occur accordingly.